1st International Workshop on Super Visualization
Description:
Supercomputing has been the major drive of the field of visualization. Visualization enables scientists to make sense of the vast amount of data generated by their massively parallel simulations. The recent advancement of GPU, Cell processors, and multi-core technologies suggests new approaches to interactive graphics and visualization, leading to another wave of active research and development in visual supercomputing. The first International Workshop on Super Visualization (IWSV08) aims at fostering exchange between visualization, graphics and HPC researchers to accelerate the development of visualization technologies for meeting the forthcoming challenges.
IWSV08 solicits submissions of papers presenting advanced prototypes, systems, algorithms, tools and environments for "Super Visualization". General survey papers indicating future directions of "Super Visualization" are also welcomed. All accepted papers will be included in workshop CD-ROM to be handed to the attendees. After the workshop, a hardcopy proceedings will be published by ACM or Springer LNCS. A small number of authors will be invited to submit an extended version of their papers to a special issue of Scientific Programming (IOS Press).
General chair:
Prof. Kazuki Joe, Nara Women's University
Duration:
Full day. Saturday June 7th, 2008
Important Dates:
1-page abstract submission deadline March 31, 2008
First stage author notification April 10, 2008
Paper submission deadline May 7. 2008
Final stage author notification (tentative) May 21. 2008
Camera-ready version deadline May 28, 2008
Final camera ready for the post-proceedings July 31, 2008
Website:
http://itolab.is.ocha.ac.jp/IWSV2008/
International Workshop on Scalable Tools for High-End Computing
Description:
Current and future high-end parallel systems will consist of hundreds of thousands of compute cores arranged in a complex hierarchical structure. Current systems, such as the Altix 4700, Blue Gene, Roadrunner, and Cray XT4, deploy multiple compute cores (homogeneous or heterogeneous) with multiple levels of shared and private caches within a processor, clustered into SMP nodes and coupled via a communication network to large scale distributed systems. The development of efficient programs is extremely complex since all the architectural details are exposed to the programmer. Productive use of such machines requires highly scalable programming tools for debugging, performance analysis, and fault tolerance. In addition, new programming models might significantly facilitate the task of the programmer.
The workshop will bring together experts on languages, compilers, and tools for parallel systems to discuss tools facilitating program development for systems with thousands of compute cores. The workshop focuses on the following topics but also submissions for other topics fitting into the overall workshop topic are welcome: performance analysis tools, debuggers, fault tolerance, programming models and interfaces and compilers. We encourage groups to submit papers giving an overview of tool projects, presenting results and experiences with using tools on High-End Systems, as well as new techniques for improving tool scalability.
Papers accepted for the workshop will be gathered in local workshop proceedings, which will allow for official publication in a conference or journal. The authors will be invited to submit extended versions after the workshop for inclusion in the Special Issue of Concurrency&Computation: Practice and Experience on Scalable Tools for High-End Computing.
Organizers:
Michael Gerndt (TU München), Jesus Labarta (Barcelona Supercomputing Center) and Barton Miller (University of Wisconsin-Madison)
Duration:
Full day. Saturday June 7th, 2008
Important Dates:
Paper submission deadline March 31. 2008
Author notification April 15. 2008
Final version for workshop proceedings April 31, 2008
Submission for C&C special issue July 31, 2008
Website:
http://www.lrr.in.tum.de/~gerndt/home/Research/ScalableToolsWorkshop/scalableTools.htm
Tutorial: Programming emerging architectures: GPUs and multicores
Description:
Graphics Processing Units (GPUs) and multicores are emerging and high dynamic architectures steadily evolving towards inexpensive parallel processors due to their high computational power and scalability at low price. This tutorial gives a comprehensive introduction to programming those novel architectures and emphasize their advantages versus existing paradigms applied to CPUs. The tutorial is organized into two parts: “Programming the GPU with CUDA” and “Programming models for multicore Cell and SMPs”.
CUDA is a new interface for programming Nvidia GPUs for general-purpose computing and hence does not suffer from constraints when accessing memory, though performance varies greatly depending on the type of memory used. This tutorial will first cover the hardware features of the GPU and its unified shaders, as well as the streaming processing paradigm in contrast with a typical CPU execution. Then CUDA will be presented, with an emphasis on its execution and memory models. For a programmer, the CUDA model is a collection of threads running in parallel which can access any memory location, but, as expected, performance boosts with the use of closer shared memory whenever data to be collectively read belong to different memory banks. Illustrating examples in the area of HPC image processing and numerical methods are used to discuss fundamental building blocks in CUDA, programming tricks, memory optimizations and performance issues on single graphics cards, multiple sockets and clusters of GPUs.
The Cell/B.E. device is composed of a 64-bit multithreaded PowerPC processor element (PPE) and eight synergistic processor elements (SPEs). Besides the complexity of dealing with several processors, the programmability of this architecture is additionally more difficult due to the non-coherence of the PPE main memory and the local memories of the SPEs. Data transfers from the main memory to the small (only 256 KB) local stores of the SPEs must be explicitly programmed. The tutorial will focus on the programming models have been recently proposed to hide this complexity. Then the focus will be on CellSs, that addresses the automatic exploitation of the functional parallelism of a sequential program through the di_erent processing elements of the Cell/B.E. architecture. The focus in on the simplicity and exibility of the programming model. Based on annotations on the source code, a source to source compiler generates the necessary code and a runtime library exploits the existing parallelism by building at runtime a task dependency graph. The runtime takes care of the task scheduling and data handling between the di_erent processors of this heterogeneous architecture. An introduction to SMPSs (tailored for homogeneous multicores) will also given.
Presenters:
Rosa M. Badia (BSC-UPC, Spain) and Manuel Ujaldon (U. of Malaga, Spain)
Duration:
Full day. Sunday June 8th, 2008
For additional information, please contact the ICS'08 Workshops and Tutorials chair Eduard Ayguade.